DK-DEV-5SGXEA7N【PDF 209/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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7-18

DQS Phase-Shift

SV51008

2014.01.10

Figure 7-5: Simplified Diagram of the DQS Phase-Shift Circuitry

This figure shows a simple block diagram of the DLL. All features of the DQS phase-shift circuitry are

accessible from the UniPHY megafunction in the Quartus II software.

addnsub

Phase offset settings

from the logic array

(offset[6:0])

7

Phase

Offset

Control

7

Phase offset

settings to DQS pins

(offsetctrlout[6:0])

DLL

aload

offsetdelayctrlout[6:0]

offsetdelayctrlin[6:0]

A

(dll_offset_ctrl_a)

Phase offset

addnsub

Control

B

Input Reference

Clock

This clock can

come from a PLL

output clock or an

input clock pin

clk

upndnin

Phase

Comparator upndninclken a

Up/Down

Counter

7

offsetdelayctrlout[6:0]

settings can only

Phase offset settings go to the DQS

from the logic array ( offset [6:0] ) logic blocks

7

Phase

Offset

Phase offset

settings to DQS pin

7 (offsetctrlout[6:0])

offsetdelayctrlin[6:0]

(dll_offset_ctrl_b)

Delay Chains

delayctrlout[6:0]

7

DQS Delay

Settings

DQS delay settings can go to the

7

dqsupdate

logic array and DQS logic block

The input reference clock goes into the DLL to a chain of up to eight delay elements. The phase comparator

compares the signal coming out of the end of the delay chain block to the input reference clock. The phase

comparator then issues the upndn signal to the Gray-code counter. This signal increments or decrements a

7-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain

to bring the input reference clock and the signals coming out of the delay element chain in phase.

Note: In the Quartus II assignment, the phase offset control block ‘ A ’ is designated as

DLLOFFSETCTRL_ CoordinateX _ CoordinateY _N1 and phase offset control block ‘ B ’ is designated as

DLLOFFSETCTRL_ CoordinateX _ CoordinateY _N2 .

The DLL can be reset from either the logic array or a user I/O pin (if 2,560 or 512 clock cycles applies). Each

time the DLL is reset, you must wait for 2,560 (low-jitter mode) or 512 clock cycles for the DLL to lock before

you can capture the data properly.

You can still use DQS phase-shift circuitry for memory interfaces running on frequencies below the minimum

DLL input frequency, which is 300 MHz. The frequency of the clock feeding the DLL should be doubled

when the interface frequency is between 150 MHz and 299 MHz or multiplied by four when the interface

frequency is between 75 MHz and 149 MHz. Because of the changes on the DLL input clock frequency, the

DQS delay chain can only shift up to 67.5° for the interface frequency between 150 MHz and 299 MHz and

33.75° for the interface frequency between 75 MHz and 149 MHz. Depending on your design, while the DQS

signal might not shift exactly to the middle of the DQ valid window, the IOE is still able to capture the data

accurately in low-frequency applications, where a large amount of timing margin is available.

For the frequency range of each DLL frequency mode, refer to the device datasheet.

Related Information

Stratix V Device Datasheet

Altera Corporation

External Memory Interfaces in Stratix V Devices

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